CMOS, The Ideal Logic Family

Category: Logic
Manufacture: Fairchild Semiconductor
Datasheet: Download this application note

CMOS, the Ideal Logic Family
CMOS, the Ideal Logic Family
INTRODUCTION Let's talk about the characteristics of an ideal logic family. It should dissipate no power, have zero propagation delay, controlled rise and fall times, and have noise immunity equal to 50% of the logic swing. The properties of CMOS (complementary MOS) begin to approach these ideal characteristics. First, CMOS dissipates low power. Typically, the static power dissipation is 10 nW per gate which is due to the flow of leakage currents. The active power depends on power supply voltage, frequency, output load and input rise time, but typically, gate dissipation at 1 MHz with a 50 pF load is less than 10 mW. Second, the propagation delays through CMOS are short, though not quite zero. Depending on power supply voltage, the delay through a typical gate is on the order of 25 ns to 50 ns. Third, rise and fall times are controlled, tending to be ramps rather than step functions. Typically, rise and fall times tend to be 20 to 40% longer than the propagation delays. Last, but not least, the noise immunity approaches 50%, being typically 45% of the full logic swing. Besides the fact that it approaches the characteristics of an ideal logic family and besides the obvious low power battery applications, why should designers choose CMOS for new systems? The answer is cost. On a component basis, CMOS is still more expensive than TTL. However, system level cost may be lower. The power supplies in a CMOS system will be cheaper since they can be made smaller and with less regulation. Because of lower currents, the power supply distribution system can be simpler and therefore, cheaper. Fans and other cooling equipment are not needed due to the lower dissipation. Because of longer rise and fall times, the transmission of digital signals becomes simpler making transmission techniques less expensive. Finally, there is no technical reason why CMOS prices cannot approach present day TTL prices as sales volume and manufacturing experience increase. So, an engineer about to start a new design should compare the system level cost of using CMOS or some other logic family. He may find that, even at today's prices, CMOS is the most economical choice. Fairchild is building two lines of CMOS. The first is a number of parts of the CD4000A series. The second is the 54C/74C series which Fairchild introduced and which will become the industry standard in the near future. The 54C/74C line consists of CMOS parts which are pin and functional equivalents of many of the most popular parts in the 7400 TTL series. This line is typically 50% faster than the 4000A series and sinks 50% more current. For ease of design, it is spec'd at TTL levels as well as CMOS levels, and there are two temperature ranges available: 54C, -55C to +125C or 74C, -40C to +85C. Table 1 compares the port parameters of the 54C/74C CMOS line to those of the 54L/ 74L low power TTL line.
Fairchild Semiconductor Application Note 77 January 1983
CHARACTERISTICS OF CMOS The aim of this section is to give the system designer not familiar with CMOS, a good feel for how it works and how it behaves in a system. Much has been written about MOS devices in general. Therefore, we will not discuss the design and fabrication of CMOS transistors and circuits. The basic CMOS circuit is the inverter shown in Figure 1. It consists of two MOS enhancement mode transistors, the upper a P-channel type, the lower an N-channel type.
FIGURE 1. Basic CMOS Inverter The power supplies for CMOS are called VDD and VSS, or VCC and Ground depending on the manufacturer. VDD and VSS are carryovers from conventional MOS circuits and stand for the drain and source supplies. These do not apply directly to CMOS since both supplies are really source supplies. VCC and Ground are carryovers from TTL logic and that nomenclature has been retained with the introduction of the 54C/74C line of CMOS. VCC and Ground is the nomenclature we shall use throughout this paper. The logic levels in a CMOS system are VCC (logic "1") and Ground (logic "0"). Since "on" MOS transistor has virtually no voltage drop across it if there is no current flowing through it, and since the input impedance to CMOS device is so high (the input characteristic of an MOS transistor is essentially capacitive, looking like a 1012 resistor shunted by a 5 pF capacitor), the logic levels seen in a CMOS system will be essentially equal to the power supplies.
1998 Fairchild Semiconductor Corporation
TABLE 1. Comparison of 54L/74L Low Power TTL and 54C/74C CMOS Port Parameters
Family VCC VIL Max 54L/74L 54C/74C 54C/74C 5 5 10 0.7 0.8 2.0 IIL Max 0.18 mA -- -- VIH Min 2.0 3.5 8.0 IIH 2.4V 10 A -- -- VOL Max 0.3 0.4 1.0 2.0 mA 360 A (Note 1) 10 A (Note 2) IOL VOH Min 2.4 2.4 9.0 100 A 100 A (Note 1) 10 A (Note 2) IOH tpd0 Typ 31 60 25 tpd1 Typ 35 45 30 PDISS/Gate Static 1 mW 0.00001 mW 0.00003 mW PDISS/Gate 1 MHz, 50 pF Load 2.25 mW 1.25 mW 5 mW
Note 1: Assumes interfacing to low power TTL. Note 2: Assumes interfacing to CMOS.
Now let's look at the characteristic curves of MOS transistors to get an idea of how rise and fall times, propagation delays and power dissipation will vary with power supply voltage and capacitive loading. Figure 2 shows the characteristic curves of N-channel and P-channel enhancement mode transistors. There are a number of important observations to be made from these curves. Refer to the curve of VGS = 15V (Gate to Source Voltage) for the N-channel transistor. Note that for a constant drive voltage VGS, the transistor behaves like a current source for VDS's (Drain to Source Voltage) greater than VGS - VT (VT is the threshold voltage of an MOS transistor). For VDS's below VGS - VT, the transistor behaves essentially like a resistor. Note also that for lower VGS's, there are similar curves except that the magnitude of the IDS's are significantly smaller and that in fact, IDS increases approximately as the square of increasing VGS. The P-channel transistor exhibits essentially identical, but complemented, characteristics.
If we try to drive a capacitive load with these devices, we can see that the initial voltage change across the load will be ramp-like due to the current source characteristic followed by a rounding off due to the resistive characteristic dominating as VDS approaches zero. Referring this to our basic CMOS inverter in Figure 1, as VDS approaches zero, VOUT will approach VCC or Ground depending on whether the P-channel or N-channel transistor is conducting. Now if we increase VCC and, therefore, VGS the inverter must drive the capacitor through a larger voltage swing. However, for this same voltage increase, the drive capability (IDS) has increased roughly as the square of VGS and, therefore, the rise times and the propagation delays through the inverter as measured in Figure 3 have decreased. So, we can see that for a given design, and therefore fixed capacitive load, increasing the power supply voltage will increase the speed of the system. Increasing VCC increases speed but it also increases power dissipation. This is true for two reasons. First, CV2f power increases. This is the power dissipated in a CMOS circuit, or any other circuit for that matter, when driving a capacitive load.
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FIGURE 3. Rise and Fall Times and Propagation Delays as Measured in a CMOS System For a given capacitive load and switching frequency, power dissipation increases as the square of the voltage change across the load. The second reason is that the VI power dissipated in the CMOS circuit increases with VCC (for VCC's > 2VT). Each time the circuit switches, a current momentarily flows from VCC to Ground through both output transistors. Since the threshold voltages of the transistors do not change with increasing VCC, the input voltage range through which the upper and lower transistors are conducting simultaneously increases as VCC increases. At the same time, the higher VCC provides higher VGS voltages which also increase the magnitude of the JDS currents. Incidently, if the rise time of the input signal was zero, there would be no current flow from VCC to Ground through the circuit. This current flows because the input signal has a finite rise time and, therefore, the input
FIGURE 2. Logical "1" Output Voltage vs Source Current

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