AN-152: FCT-T Octal Logic Characteristics...
Manufacture: Integrated Device Technology, Inc.
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FCT-T OCTAL LOGIC CHARACTERISTICS AND APPLICATIONS
Integrated Device Technology, Inc.
APPLICATION NOTE AN-152
IDT FCT Octal Logic is form, fit, and function compatible with other industry standard logic families, but will provide a significant performance improvement in most applications. IDT's FCT Octal Logic is available in a variety of configurations, allowing the designer to select the proper component for the application. This application note is intended to be used as a designer's guide to component selection and usage. The data contained within this document is typical data taken at 25oC and 5.0V Vcc, except where otherwise noted. The data has been derived from component characterization where in most cases, the component selected is a `244 type. The data is intended as a design guideline only. For "guaranteed" specifications the IDT Logic Data Book provides full specifications over Vcc, temperature and process.
OCTAL LOGIC FAMILIES ......... Gate Array Design Approach ..... DC ELECTRICAL CHARACTERISTICS .. Input Characteristics .... Unused and Floating Inputs ........... Output Characteristics .......... High Drive Output Structure ........... Balanced Drive Output Structure .... CMOS Drive Output Structure ........ Comparison with Double Density ... Connecting Outputs Together ........ Bus Contention ....... I/O Port Characteristics ........ AC ELECTRICAL CHARACTERISTICS .. Delay as a Function of Supply Voltage ........ Performance Under Temperature ....... Rise and Fall times ...... Delay Vs Load .... Number of Outputs Switching ..... Output Enables, Setup/Hold Times ..... Setup and Hold Times ..... Metastability ....... POWER DISSIPATION .... Leakage Currents (Icc) ......... Dynamic Switching Current (Iccd) ....... Input Leakage (DIcc) ... Load Currents ..... CONCLUSIONS ...... 15 15 15 16 16 17 17 17 18 19 19 19 19 20 20 20 21 21 22 22 23 23 23 23 24 24 24 24
and functionality uniformity is maintained across the families, allowing plug in replacement if a family transition is required. All FCT logic comes in a variety of speed grades, allowing plug in replacement for performance upgrades or a downgrade for cost savings. The speed grades are uniform across all FCT families including the 16 bit Double Density and 3.3V families. The Octal FCT Logic families can be divided into three distinct groups: 1) FCTxxxT, High Drive 2) FCT2xxxT, Balanced Drive 3) FCTxxx, CMOS Drive High Drive has TTL level outputs with -15/64mA drive capability. High Drive is intended for driving heavily loaded busses and backplanes where significant current levels are required. The TTL level outputs, give lower noise levels and faster switching speeds than can be obtained with similar CMOS rail swing components. High drive has Power-off Disable, making the family ideal for partially powered applications or situations where an interface may become connected/ disconnected while powered. Balanced Drive Octals also have TTL level outputs with a drive capability of -15/12mA. Internal series resistors on Balanced Drive reduce the drive and noise levels, giving superior low noise performance on moderately to lightly loaded busses. The series resistors provide source termination, eliminating the need for external series resistors in most applications. Balanced Drive is ideal as a general use family. The CMOS output components have full rail to rail output voltage swing with TTL level input thresholds. These components are intended only for applications requiring the CMOS rail swing output voltages. The High Drive and Balanced Drive TTL level components with lower voltage switching levels will provide higher performance, lower noise, and lower dynamic power dissipation. Gate Array Design Approach FCT logic is built using standard gate arrays with a "sea of gates". The arrays are uniform across products of similar pin count, but allow a final metal mask variation which gives the unique part type logic characteristics. In addition, the final metal mask allows a selection of output characteristics, allowing a single array type to provide all families including High Drive, Balanced Drive and CMOS. Using the standard gate array approach, IDT maintains a high level of consistency from component to component and logic family to logic family. This eases component qualification for most users because a single qualification makes available a wide variety of products.
IDT's Octal Logic includes several families, each with specific target applications. Consistent among all of the families is the high speed and very low power dissipation. Pin
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DC ELECTRICAL CHARACTERISTICS
Included in the DC Electrical Characteristics are device
FCT-T OCTAL LOGIC CHARACTERISTICS AND APPLICATIONS
APPLICATION NOTE AN-152
input and output impedances, drive capabilities and breakdown limitations. The guaranteed DC test limits are shown in the IDT Logic Data Book in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table and OUTPUT DRIVE CHARACTERISTICS table for each component. When calculating loading, drive capabilities, power dissipation and line termination needs, additional information beyond the data book specifications is often required. This information is supplied here. Input Characteristics The input structure of all IDT FCT logic is shown in Figure 1. The structure consists of the gates to a P-Channel and an N-Channel FET. A parasitic clamp diode connects the input to ground, but there is no clamp diode to Vcc associated with the input. Components that combine an input with an output (forming an I/O port) may have a clamp to Vcc depending upon the type of output structure selected.
The input threshold voltage for FCT-T logic is set at a nominal 1.5V with Vcc = 5.0V. As can be seen in Figure 2, the input threshold will vary relative to Vcc with the input hysteresis causing the slight difference between Vih and Vil. The data sheet limit for Vil is >0.8V and the limit for Vih is <2.0V. These values are guaranteed when Vcc is between 4.5V and 5.5V. Figure 3 shows the V/I curve for device inputs. As the input voltage drops below -0.7V the effect of the input clamp can be seen as the input current level increases dramatically. Within the normal operating range of -0.5V to 5.5V, the input current typically is <0.1uA. As the input voltage increases beyond the absolute maximum rating (7.0V), the device will begin breakdown. This typically occurs at some level beyond 12 volts and may cause damage to the component.
-8 -10 -2 0 4 6 8 10 Input Voltage (Volts) Figure 3, Input Impedance 2 12 14
Figure 1, Input Structure
Contained within the input structure is a hysteresis circuit that provides a weak positive feedback into the input causing a small difference between Vih (logic HIGH threshold) and Vil (logic LOW threshold). This helps to reduce noise induced switching and oscillations that may occur when the input voltage level hovers near the input toggle point.
Input Threshold Voltage (Volts)
2.40 2.00 1.60 1.20 VIL 0.80 0.40 0.00 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00 Vcc (Volts) VIH
Figure 2, Input Threshold Voltage (Vih/Vil)
Unused and Floating Inputs Because of the high input impedance of CMOS components an input will not drive itself to a valid logic state. Inputs left floating may float near the logic threshold and cause power dissipation as shown in Figure 29. In addition, if the input is picking up a low level, high frequency noise, the input stage may toggle causing the component to oscillate. If the oscillating frequency becomes extreme, the power dissipation of the component may reach high levels, eventually causing device failure. Special problems may occur with inverting components that have floating inputs. As a floating input toggles the device, the reverse direction of the output switching on an inverter may cause a temporary shifting of the ground reference (ground bounce). A change in ground reference may change the input toggle voltage, causing it to pass back through the floating input voltage. As this back and forth ground shifting continues, the device may go into a high frequency oscillation. Input hysteresis which is present on all FCT logic should mitigate many of the oscillation effects caused by noise on a floating input, slowly rising/falling input signals, and bounce, but a typical 200mV hysteresis level is not sufficient to fully overcome these effects. Unused inputs should be tied directly to Vcc or GND to