AN-147: The Myth of Ground Bounce Measurements

Category: Logic
Manufacture: Integrated Device Technology, Inc.
Datasheet: Download this application note

Integrated Device Technology, Inc. By Stanley Hronik
Ground Bounce is one of the primary causes of false switching in high speed components and is a major cause of poor signal quality. While ground bounce is easily measured on CMOS components, an accurate measurement is somewhat elusive on bipolar or BiCMOS components. For components with a bipolar or BiCMOS output structure, any reading obtained through standard ground bounce tests will be several hundred milivolts low. This is due to the inability of these components to hold a solid logic low level with low impedance. The accompanying characteristic of Vcc bounce is less troublesome than ground bounce, but will have a greater influence as Vcc levels drop to 3.3V, 2.5V and lower. Vcc bounce is easily measured only on components that have a CMOS rail swing output. Since there is no direct connection to Vcc in any component except components with CMOS rail swing outputs, the measurement of Vcc bounce is not directly possible in many standard logic families.
Ground Bounce is a voltage oscillation between the ground pin on a component package and the ground reference level on the component die. Essentially it is caused by a current surge passing through the lead inductance of the package. The effect is most pronounced when all outputs switch simultaneously, (hence the alternate name, Simultaneous Switching Noise). While the inductance is the combined effect of the package lead, the package lead frame, the bond wire and the inductance in the die pad, most of the inductance is caused by the bond wire. Figure 1 shows a typical waveform for a high speed CMOS component with TTL level outputs. Shown directly above the signal waveform on the same time scale is the voltage seen on the ground of the die relative to the external ground. Directly above that is the voltage seen on the die Vcc relative to the external Vcc on the board.
GROUND BOUNCE DESCRIPTION ...... 89 The Ground Bounce Effect in CMOS .. 90 The Ground Bounce Effect in BiCMOS .... 90 PROBLEMS CREATED BY BOUNCE ... 91 False Switching .. 91 Poor Signal Quality ..... 93 BOUNCE MEASUREMENTS ........ 93 Traditional Ground Bounce Measurements ....... 93 Accurate Ground Bounce Measurements ......... 93 Measuring Vcc Bounce ..... 94 BOUNCE INFLUENCES ...... 94 Drive Level Effect on Ground Bounce ....... 94 Fast Edge Rates ......... 95 Crossover Current ....... 95 Package Effect on Ground Bounce ..... 96 Double Density Packaging ......... 96 Octal Packaging .......... 96 Load Effect on Ground Bounce .. 96 DESIGN CONSIDERATIONS ....... 96 Choose the Right Driver .... 96 Avoid Pull Up Resistors on BiCMOS ... 97 OE with Clock HIGH .... 97 Slow Clock Edges ....... 97 Bus Inverting Components ......... 97 Use Bus-hold ..... 97 Avoid Ground Bounce in Memory Arrays .......... 98 CONCLUSION ...... 98
Vcc voltage level on the die 5 Vohv
Volp Die Ground voltage
0.5 0 -0.5 -1 -1 0 1 2 3 4 5 678 Time (ns) 9 10 11 12 13 14 15
Figure 1, Ground Bounce
As shown in Figure 1, ground bounce and Vcc bounce cause signal degradation in the output waveform of the device. This consists of an undershoot and overshoot on both the rising and falling edges of the waveform.
The IDT logo is a registered trademark of Integrated Device Technology, Inc. 1996 Integrated Device Technology, Inc. 3574/-
There are four parameters for measuring ground bounce and Vcc bounce which are identified in Figure 1. In the order of significance they are: Volp -- peak voltage of the ground bounce, Volv -- valley voltage of the die ground during bounce Vohv -- negative voltage change in Vcc during bounce Vohp -- peak voltage change in Vcc during bounce When reading specifications for ground bounce, the parameter most often used to identify the ground bounce level is Volp. In statements such as "Ground Bounce = XX volts", this is the parameter being referenced. Ground Bounce levels are typically more pronounced than Vcc Bounce levels because of the HIGH to LOW transition is trying to quickly bring a HIGH signal down to a narrow window of <400mV for a logic LOW. A low output impedance is required to complete the transition quickly. In the LOW to HIGH, the only requirement is that the output be above 2.4V. 5V is available as a driving voltage. A much lower pull up impedance is required to make the transition quickly. The Ground Bounce Effect in CMOS The output structure for a CMOS component with TTL level outputs is shown in Figure 2. In addition to the structure shown, the output contains resistors in most components which will dampen the output waveforms and reduce the effects of ground bounce and Vcc bounce. In order to simplify the drawings and discussion, these have been eliminated from the drawing.
DIE Boundary Package Boundary
80 60 40 20 0 -20 -40 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 Volts 0.5 0.6 0.7 0.8 0.9 1.0
Figure 3, FCT Output VI Curve for Vol
As a CMOS component makes a transition from a HIGH to a LOW as shown in Figure 4, the pull down FET will lock (6.5 impedance) the device output to Die GND in Figure 2. To accomplish this task, the pull down FET will be required to discharge the internal capacitances of the die. This causes a sudden surge of current from the Die GND to the Board GND. The current surge then causes a voltage drop across the ground lead inductance. If all device outputs switch simultaneously, the instantaneous current through the ground lead inductance can be significant.
-2 -1 0 1 2 3 4 5 Time (ns) 6 7 8 9 10
Figure 4, Undershoot in CMOS from Ground Bounce
Figure 2, CMOS Device Output Structure
There is a clamp diode between the device output and the Die GND on all CMOS components. In ground bounce discussions, this clamp diode can be ignored. During HIGH to LOW transitions, the pull down FET will be at a very low impedance from drain to source. Transitions of the Output below ground will be caused by a voltage drop across the lead inductance and will not forward bias the clamp diode. Figure 3 shows the VI curve for a typical FCT High Drive CMOS component with TTL output levels. The curve is very flat at 6.5 throughout the operating region around zero volts. This flatness continues below zero until the effect of the clamp diode to Die GND takes effect at about -0.7V.
Figure 4 shows the waveform visible to the outside world from a HIGH to LOW transition. The transition is clean from the Voh level to zero, but the lead inductance continues to cause ringing. With an N-Channel FET pull down, the output will be tied closely to the Die GND regardless of whether the Die GND is above or below the Board GND. The Ground Bounce Effect in BiCMOS BiCMOS components have a different output structure than CMOS components and have significantly higher ground bounce than CMOS due to a much faster edge rate, lower output impedance, and the lack of a control on signals that overshoot. As a result the noise generated has different effects than CMOS components.

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