AN-20: Board Assembly for 0.4mm Pin Surface Mounts
Manufacture: Integrated Device Technology, Inc.
Datasheet: Download this application note
QUALITY SEMICONDUCTOR, INC.
Board Assembly Techniques for 0.4mm Pin Pitch Surface Mount Packages
Application Note AN-20
The need for higher performance systems continues to push both silicon and packaging technologies to new advances. As an example, in 1991 Quality Semiconductor (QSI) introduced the QSOP (Quarter Size Outline Package) package that provided system designers with the highest density package for interface logic devices. The QSOP used a combination of existing technologies to provide a very small, cost effective solution for systems with limited board area. By using the same assembly mold tooling as the narrow body (150-mil) SOIC and designing a lead frame with a standard 25-mil pin pitch, QSI was able to provide the same functionality as a 300-mil wide SOIC in one fourth the space. All of this was accomplished without pushing the state of the art in circuit board assembly technology. Subsequent generations of QSI packages will maintain this philosophy, including the 40- and 48-pin QVSOPTM packages, which provide double width logic in the same form factor as the 28-pin QSOP. Another advanced package is the industry standard 120-pin TQFP for specialty memory devices. The 40-pin QVSOP has a pin pitch of 0.5mm which can be manufactured using standard surface mount techniques. However, because the pin pitch of the 48-pin QVSOP and the 120pin TQFP is 0.4mm, additional care must be used in the printed circuit board (PCB) assembly process. The purpose of this application note is to outline the basic board assembly operation using fine pitch packages and provide detail on each portion of the operation as it pertains specifically to packages with 0.4mm pin pitch.
body size. This savings of cost and time extends to test handlers and shipping tubes, during device test and to tape and reel equipment and lead scan equipment during final preparation for shipment. From the board assembly standpoint, component placement equipment need not be modified to accommodate a new body size. This packaging development philosophy has extended to QSI's next generation of packaging. The 48-pin QVSOP utilizes the same body, hence assembly mold, as the 16-pin narrow SOIC and the 28pin QSOP. The QVSOP uses the same manufacturing equipment as the QSOP as well. Using the existing manufacturing tools means lower development costs will be incurred and lower costs can be passed on to the end user. By using a pin pitch of 0.4mm, a new level of system density can been achieved with the 48-pin QVSOP. This is illustrated in Figure 1. With this new level of system density comes a few new challenges during the board assembly process that can be overcome using some slightly different PCB manufacturing techniques.
SMT Board Manufacturing Primer
The simplified model of the board assembly process is divided into four sections and each will be discussed in detail. Board layout, the first portion, begins before the board is manufactured. Critical issues at this stage are design and layout philosophy, and board manufacturing capabilities. After the board has completed layout and manufacture, solder must be deposited on the board as the next step in the process. Once the solder is on the board, each component is placed on the board and the solder is reflowed to create reliable solder joints between the component leads and the circuit board. The last step in the process, rework, is necessary only if there are any soldering defects from the previous steps in the process. This article will start with the basic PCB manufacturing flow used with 25-mil pin pitch devices and will provide information to enhance this flow to incorporate the use of 15-mil (0.4mm) pin pitch devices.
QSI's Packaging Uses Existing Manufacturing Tools
QSI's approach to new package development keeps in mind both the need to provide higher density packages to its customers and the need to minimize new package start up costs. The QSOP uses all of the same manufacturing equipment as the narrow SOIC from packaging assembly to placement on the circuit board. The assembly mold for the 20- and 24pin QSOP, which is used to form the plastic around the silicon die, is the same mold used for the 14-pin narrow SOIC. This eliminated the cost, and time, of developing an entirely new mold for a non-standard
QUALITY SEMICONDUCTOR, INC.
AN-20 Layout With Rework Capability Minimizes Cost
A common argument used against higher density packaging is that the smaller space is of no benefit because the vias used to interconnect between board layers no longer fit under the package. This argument is only valid if no rework capability is designed into the circuit. However, as package geometries shrink, circuit rework and testability issues become even more important. A PCB layout technique called cut, etch and rewire provides a low cost method for quickly modifying PCB's and takes full advantage of the board space savings that fine pitch packages such as the QVSOP provide. Cut, etch and rewire requires that there be a top layer etch run that separates the device pad from the PCB via. Any pin can then be removed from the circuit and rewired to either a bond pad or a via. This technique is described in detail in QSI's application note AN-19.
Figure 1. Relative Area of 16 Bit Packaging Solutions
0.008 All Dimensions in Inches
Figure 2. 48-pin QVSOP Footprint
QUALITY SEMICONDUCTOR, INC.