AN-123: ESD Considerations in High Speed Circuits

Category: Logic
Manufacture: Integrated Device Technology, Inc.
Datasheet: Download this application note

Integrated Device Technology, Inc. By Stanley Hronik
The primary cause of component failure in high speed logic circuits is electrostatic discharge (ESD)1. ESD can be encountered during improper device or board handling, through improperly designed interfaces, or if lightning or other phenomena causes a large voltage spike on a device interface. The industry has adopted standards and methods for component handling, system design, and component design which avoid many of the potential problems with ESD. When devices are damaged by static electricity, the affected devices may cease to function, exhibit parameter degradation, or demonstrate high failure rates. In all situations the only repair is the replacement of the damaged component. storage tube to a grounded surface. Human Body Model The human body model, the model most often referred to in component data sheets when an ESD rating is given, is shown in Figure 1. The model consists of a voltage source that charges a 100pF capacitor. When the capacitor is at full charge, the capacitor is then discharged through a 1500 current limiting resistor into the device under test. The test is conducted with the device under test connected in the following configurations:
ESD MODELS Human body model .... 104 Machine model .. 105 Charged Device Model .......... ... 105 ESD rating classes ..... 105 ESD RATING OF IDT LOGIC COMPONENTS ESD structure in IDT logic components.... 105 COMPONENT ESD VULNERABILITY Loose components ..... 106 Board and system assemblies ... 106 DESIGNING FOR ESD ENVIRONMENTS External cable connections ........ 107 Line termination .......... 107 Transient suppression devices .. 107 Optocouplers ..... 108 Common mistakes ...... 108 CONCLUSIONS .... 108
All pins with respect to ground. Terminal B is connected to all device ground pins. Terminal A is connected to each non ground pin individually and the test is run for each pin. All other pins are open.
All pins with respect to power. The test is repeated except terminal B is connected to all power (Vcc) pins. If there is more than one type of power supply (e.g. two voltage levels), each group of power pins is connected to terminal B independently. All other pins are open.
Pins with respect to others on the same interface. The test is repeated except terminal B is connected to all other pins with a name similar to the one under test. e.g. If a pin on an output port is being tested, all other pins in the same port are connected to terminal B. All other pins are open.
1-10M Terminal A Test Voltage 100pF Device Under Test 1500 Terminal B
In order to establish industry standards and provide uniformity between manufacturers on ESD ratings, models have been developed for testing devices under closely controlled conditions in ESD simulated environments. The first model is the Human Body Model which is designed to simulate the high impedance contact made when touching components with the hand or in similar situations. The second model is the Machine Model which simulates a much lower contact impedance as may be experienced in a component handler or similar situation where the device contacts are touching other metal. The third model is the Charged Device Model that simulates passing components between charge levels as may happen when a component is dropped from a statically charged
The IDT logo is a registered trademark of Integrated Device Technology Inc. 1996 Integrated Device Technology Inc.
Figure 1. Human Body Model for ESD testing.
The tests are conducted with the device receiving three positive voltage pulses and three negative voltage pulses in each configuration. All component configurations must be able to withstand the test voltage for the component to be rated at the test voltage. Component damage can determined by the failure to pass any component test, but is usually exhibited by excessive leakage currents. Machine Model The Machine Model as shown in Figure 2 is similar to the Human Body Model except the Machine Model contains a larger capacitor and there is no series resistor to limit the current levels. With the higher current levels in the Machine Model, most components will break down at much lower test voltages than with the Human Body Model.
1-10M Terminal A Test Voltage 200pF Device Under Test
ESD Rating Classes The ESD rating classes are defined in Mil-Std-883C, Method 3015.7 and are as follows using the human body model: ESD Failure Thresholds Class 1 -- 0 volt to 1999 volts Class 2 -- 2000 volts to 3999 volts Class 3 -- 4000 volts and above
The ESD rating levels of IDT Logic Components are achieved through the integrity of the array on which the parts are built. All of IDT's newer arrays have class 2 ESD protection (>2000V human body model, >200V machine model). To achieve and guarantee class 2 levels, the ESD breakdown level on newer logic components is typically 3500 - 4000 volts human body model. IDT Logic Components which are guaranteed to have class 2 ESD ratings typically have a note listed in the FEATURES section of the data sheet as follows: ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0). The "Absolute Maximum Ratings" table in IDT data sheets lists the maximum voltages IDT Logic Components can withstand for extended periods. Since ESD voltages exceed those, exposure to ESD will cause damage to the device if the voltages are extreme, if the charge density is too high, or if the component is repeatedly exposed to high voltage levels. Exposure to ESD can have cumulative effects and eventually cause breakdowns, even if the component is rated for the exposure voltage. ESD Structure in IDT Logic Components The ESD rating level on IDT Logic Components is achieved through the device technology. Various models show what may happen under several ESD situations. Since ESD is unpredictable in its intensity, source, polarity, and discharge path, the models represent idealized situations and may or may not represent the effects of selected situations. IDT Logic Components contain various pin and device dependent ESD structures. A partial model of these ESD structures is shown in Figure 4. The clamp diodes on the component inputs and outputs serve as the primary bypass paths for ESD charge currents. If an ESD charge forward biases one of the clamp diodes, the clamp diode drains off the excess charge and relieves the charge voltage. Ideally this is done without damaging the component. The source impedance, lead inductance, input capacitance and silicon structure all serve to protect the component from ESD damage.
Figure 2. Machine Model for ESD testing.
Charged Device Model The Charged Device Model, as shown in Figure 3, statically charges the component with a high voltage power supply through the 500M resistor to the test voltage with the connection to the 1 resistor open. When fully charged, the connection to the voltage source is broken and the connection to ground is made through the 1 resistor. The test can be conducted between any two device pins or using the same pin for both the charge and discharge path. The 1 resistor allows the connection of a 50 scope probe to view the output waveform and measure the current levels. The current levels are determined by the capacitance levels of the device under test.
Device Under Test 500M High Voltage 1
Figure 3. Charged Device Model for ESD testing.

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