AN-01: Ground Bounce Noise in TTL Logics

Category: Logic
Manufacture: Integrated Device Technology, Inc.
Datasheet: Download this application note

Ground Bounce Noise in TTL Logic
Application Note AN-01
High-speed TTL octal drivers such as the FCT244 can generate ground bounce noise when driving capacitive loads at high-speed. On the FCT244, ground bounce occurs when seven of the eight outputs are switching HIGH-to-LOW with a high capacitance load, and the eighth output is held a constant LOW. In this case, the HIGH-to-LOW transition of the outputs causes capacitive current (I = CdV/dt) to flow in the single ground lead of the FCT244. This current pulse causes a voltage pulse to appear (V = Ldi/dt) across the package inductance of the ground lead. This voltage pulse on the unchanging LOW output is called ground bounce noise. This voltage pulse will appear on the output that is held LOW, since it shares the common ground pin. Ground bounce noise is a concern of the system designer because it can affect other circuits in a
design. Ground bounce is a chip design problem with system implications. The chip designer tries to achieve the highest speed with an acceptable level of ground bounce. The system designer needs to understand the limits of the combination of chip and package technology represented by ground bounce to know what to expect from future designs. A ground bounce model is a useful tool for achieving these goals. In this paper, we will study ground bounce using an RLC resonant circuit model.
Ground Bounce Example
Figure 1 shows a test setup which allows ground bounce to be measured, and Figure 2 shows typical results.
FCT244 TTL Octal Driver
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 50pF Oscilloscope 50pF 50pF 50pF 50pF 50pF
Figure 1. Ground Bounce Test Setup
MAPN-00001-00 NOVEMBER 3, 1997
bounce is an indirect problem in these cases to the extent that it increases system noise and corresponding settling times in general.
Ground bounce noise is a problem only if it affects the circuits it drives. Whether driven circuits are affected is determined by the difference between the ground bounce pulse size and duration and the dynamic (AC) noise margin of the driven circuit. Dynamic noise margin is a function of the logic family of the driven circuit: i.e., LS, AS, F, HCT, etc. A plot of dynamic noise margin for various TTL logic families and showing typical ground bounce pulses is shown in Figure 3. Ground bounce is associated with HIGH-to-LOW switching in TTL designs. In the HIGH-to-LOW (ground bounce) case, the unswitched output is connected directly to ground. The ground bounce spike from the internal ground is coupled directly to the output. In the LOW-to-HIGH (VCC bounce) case, the unswitched output is either connected directly to the internal VCC in a CMOS output or buffered from VCC by a source- or emitter-follower transistor in the TTL output case. In the CMOS output case, the VCC bounce noise margin is (5-1.5) = 3.5V, more than twice the ground bounce margin. In the TTL output case, the source/emitter-follower buffer isolates the VCC bounce from the actual output.
Figure 2. Ground Bounce Noise Oscilloscope Trace
Problems Caused by Ground Bounce in TTL System Designs
Ground bounce noise is a problem when it couples into other circuits or when it upsets the operation of the IC that generates it. Ground bounce noise is a problem in bus driver chips when the unswitched output is a control signal used to enable or clock other circuits. Ground bounce is not a problem in data or address bus driver circuits where all outputs switch and settle at the same time and their associated circuitry waits until the signals are settled before sampling them. Ground
Pulse Amplitude, Volts
Figure 3. Dynamic Noise Margin of Various TTL Logic Families 2 QUALITY SEMICONDUCTOR, INC. MAPN-00001-00 NOVEMBER 3, 1997

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